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mb95260h/270h/280h series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-07516 rev. *b revised august 24, 2017 mb95260h/270h/280h are series of general-pur pose, single-chip microcontrollers. in a ddition to a compact instruction set, the microcontrollers of these series cont ain a variety of peripheral resources. features f 2 mc-8fx cpu core instruction set opti mized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instructions bit manipulation instructions, etc. clock (main osc clock and sub-osc clock are only available on mb95f262h/ f262k/f263h/f263k/f264h /f264k/f282h/f282k/f283h/f283k/f284h/f284k) selectable main clock source ? main osc clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (1/8/10 mhz ? 3%, maximum machine clock frequency: 10 mhz) selectable subclock source ? sub-osc clock (32.768 khz) ? external clock (32.768 khz) ? sub cr clock (typ: 100 khz, min: 50 khz, max: 200 khz) timer 8/16-bit composite timer time-base timer watch prescaler lin-uart (only available on mb95f262h/f262k /f263h/f263k/f264h/f264k/f282h/f282k/f283h /f283k/f284h/f284k) full duplex double buffer capable of clock-synchronized serial data transfer and clock-asynchronized se rial data transfer external interrupt interrupt by edge detection (rising edge, falling edge, and both edges can be selected) can be used to wake up the device from different low power consumption (standby) modes 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected. low power consumption (standby) modes stop mode sleep mode watch mode time-base timer mode i/o port (max: 17) (mb95f262k/f263k/f264k) general-purpose i/o ports (max): cmos i/o: 15, n-ch open drain: 2 i/o port (max: 16) (mb95f262h/f263h/f264h) general-purpose i/o ports (max): cmos i/o: 15, n-ch open drain: 1 i/o port (max: 5) (mb95f272k/f273k/f274k) general-purpose i/o ports (max): cmos i/o: 3, n-ch open drain: 2 i/o port (max: 4) (mb95f272h/f273h/f274h) general-purpose i/o ports (max): cmos i/o: 3, n-ch open drain: 1 i/o port (max: 13) (mb95f282k/f283k/f284k) general-purpose i/o ports (max): cmos i/o: 11, n-ch open drain: 2 i/o port (max: 12) (mb95f282h/f283h/f284h) general-purpose i/o ports (max): cmos i/o: 11, n-ch open drain: 1 on-chip debug 1-wire serial control serial writing supported (asynchronous mode) hardware/software watchdog timer built-in hardware watchdog timer built-in software watchdog timer power-on reset a power-on reset is generated when the power is switched on. low-voltage detection reset circuit built-in low-voltage detector
mb95260h/270h/280h series document number: 002-07516 rev. *b page 2 of 92 clock supervisor counter built-in clock supervisor counter function programmable port input voltage level cmos input level / hysteresis input level dual operation flash memory the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. flash memory security function protects the content of the flash memory
mb95260h/270h/280h series document number: 002-07516 rev. *b page 3 of 92 contents product line-up ................................................................ 4 packages and corresponding products ........................ 9 differences among products and note ........................... s on product selection ...................................................... 10 pin assignment .............................................................. 11 pin description (mb95260h series, 32 pins) ............... 13 pin description (mb95260h series, 24 pins) ............... 15 pin description (mb95260h series, 20 pins) ............... 17 pin description (mb95270h series, 8 pins) ................. 19 pin description (mb95280h series, 32 pins) ............... 20 pin description (mb95280h series, 16 pins) ............... 22 i/o circuit type ............................................................... 24 notes on device handling ............................................. 26 pin connection ............................................................... 26 block diagram (mb95260h series ) ................ ........... .... 28 block diagram (mb95270h series ) ................ ........... .... 29 block diagram (mb95280h series ) ................ ........... .... 30 cpu core ......................................................................... 31 i/o map (mb95260h series) ....... .............. .............. ........ 32 i/o map (mb95270h series) ....... .............. .............. ........ 36 i/o map (mb95280h series) ....... .............. .............. ........ 40 interrupt source table (mb95260h series) .................. 44 interrupt source table (mb95270h series) .................. 45 interrupt source table (mb95280h series) .................. 46 electrical characteristics ............................................... 47 absolute maximum ratings ... .................................... 47 recommended operating conditions ....................... 49 dc characteristics .................................................... 50 ac characteristics ..................................................... 53 a/d converter ............................................................ 68 flash memory program/erase characteristics .......... 72 sample characteristics .................................................. 73 mask options .................................................................. 79 ordering information ...................................................... 80 package dimension ........................................................ 82 major changes ................................................................ 90 document history ........................................................... 91
mb95260h/270h/280h series document number: 002-07516 rev. *b page 4 of 92 1. product line-up mb95260h series (continued) part number parameter mb95f262h mb95f263h mb95f264h mb95f262k mb95f263k mb95f264k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected by software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61. 5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o ports (max) : 16 ? cmos i/o : 15 ? n-ch open drain : 1 ? i/o ports (max) : 17 ?cmos i/o :15 ? n-ch open drain : 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? clock-synchronized serial data transfer and clock- asynchronized serial data transfer is enabled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 6 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". ? it has built-in timer function, pwc function, pwm function and input capture function. ? count clock: it can be select ed from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing. (asynchronous mode)
mb95260h/270h/280h series document number: 002-07516 rev. *b page 5 of 92 (continued) part number parameter mb95f262h mb95f263h mb95f264h mb95f262k mb95f263k mb95f264k watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming, embedded algorith m, program/erase/erase-suspend/erase-resume com- mands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? number of program/erase cycles: 100000 ? data retention time: 20 years ? flash security feature for protec ting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package dip-24p-m07 lcc-32p-m19 fpt-20p-m09 fpt-20p-m10
mb95260h/270h/280h series document number: 002-07516 rev. *b page 6 of 92 mb95270h series part number parameter mb95f272h mb95f273h mb95f274h mb95f272k mb95f273k mb95f274k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected by software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61. 5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o ports (max) : 4 ? cmos i/o : 3 ? n-ch open drain : 1 ? i/o ports (max) : 5 ?cmos i/o :3 ? n-ch open drain : 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-internal cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. lin-uart no lin-uart 8/10-bit a/d converter 2 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 1 channel ? the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". ? it has built-in timer function, pwc function, pwm function and input capture function. ? count clock: it can be select ed from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 2 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing. (asynchronous mode) watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming, embedded algorit hm, program/erase/erase-suspend/erase-resume com- mands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? number of program/erase cycles: 100000 ? data retention time: 20 years ? flash security feature for protecti ng the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package dip-8p-m03 fpt-8p-m08
mb95260h/270h/280h series document number: 002-07516 rev. *b page 7 of 92 mb95280h series (continued) part number parameter mb95f282h mb95f283h mb95f284h mb95f282k mb95f283k mb95f284k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected by software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o ports (max) : 12 ? cmos i/o : 11 ? n-ch open drain : 1 ? i/o ports (max) : 13 ?cmos i/o :11 ? n-ch open drain : 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-internal cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? clock-synchronized serial data transfer and clock- asynchronized serial data transfer is enabled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 5 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 1 channel ? the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". ? it has built-in timer function, pwc functi on, pwm function and in put capture function. ? count clock: it can be select ed from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing. (asynchronous mode)
mb95260h/270h/280h series document number: 002-07516 rev. *b page 8 of 92 (continued) part number parameter mb95f282h mb95f283h mb95f284h mb95f282k mb95f283k mb95f284k watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming, embedded algorit hm, program/erase/erase-suspend/erase-resume com- mands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? number of program/erase cycles: 100000 ? data retention time: 20 years ? flash security feature for protecti ng the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package lcc-32p-m19 dip-16p-m06 fpt-16p-m06
mb95260h/270h/280h series document number: 002-07516 rev. *b page 9 of 92 2. packages and corresponding products o: available x: unavailable part number package mb95f2 62h mb95f2 62k mb95f2 63h mb95f2 63k mb95f2 64h mb95f2 64k mb95f2 72h mb95f2 72k mb95f2 73h mb95f2 73k mb95f2 74h mb95f2 74k dip-24p-m07 oooooox x x x x x fpt-20p-m09 oooooox x x x x x fpt-20p-m10 oooooox x x x x x dip-16p-m06 xxxxxxxxxxxx fpt-16p-m06 xxxxxxxxxxxx dip-8p-m03 xxxxxxoooooo fpt-8p-m08 xxxxxxoooooo lcc-32p-m19 oooooox x x x x x part number package mb95f282h mb95f282k mb95f283h mb95f283k mb95f284h mb95f284k dip-24p-m07 x x x x x x fpt-20p-m09 x x x x x x fpt-20p-m10 x x x x x x dip-16p-m06 oooooo fpt-16p-m06 oooooo dip-8p-m03 xxxxxx fpt-8p-m08 x x x x x x lcc-32p-m19 oooooo
mb95260h/270h/280h series document number: 002-07516 rev. *b page 10 of 92 3. differences among products and not es on product selection current consumption when using the on-chip debug function, take account of the current consumption of flash erase/write. for details of current consumption, se e ?24. electrical characteristics?. package for details of information on each package, see ?2. packa ges and corresponding products? and ?28. package dimension?. operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of the operating voltage, s ee ?24. electrical characteristics?. on-chip debug function the on-chip debug function requires that v cc , v ss and 1 serial-wire be connected to an evaluat ion tool. in addition, if the flash memory data has to be updated, the pf2/rst pin must also be connected to the same evaluation tool.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 11 of 92 4. pin assignment (continued) p12/ec0/dbg nc p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 nc p64/ec1 x0/pf0 nc x1/pf1 vss x1a/pg2 x0a/pg1 vcc c rst/pf2 to10/p62 nc to11/p63 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 p64/ec1 x0/pf0 x1/pf1 vss x1a/pg2 x0a/pg1 vcc c rst/pf2 to10/p62 to11/p63 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 p64/ec1 x1/pf1 x0/pf0 vss x1a/pg2 x0a/pg1 vcc c rst/pf2 to10/p62 nc nc nc nc nc nc nc nc nc nc nc nc to11/p63 20 21 22 23 24 32 31 30 29 28 27 26 25 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 910 (top view) 24 pins dip-24p-m07 the number of usable pins is 20. (top view) 32 pins lcc-32p-m19 the number of usable pins is 20. (top view) 20 pins fpt-20p-m09 fpt-20p-m10
mb95260h/270h/280h series document number: 002-07516 rev. *b page 12 of 92 (continued) p12/ec0/dbg p06/int06/to01 p05/an05/to00 p04/int04/an04/ec0 vss vcc c rst/pf2 8 7 6 5 1 2 3 4 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p01/an01 p02/int02/an02/sck x0/pf0 x1/pf1 vss x1a/pg2 x0a/pg1 vcc rst/pf2 c 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 x1/pf1 x0/pf0 vss x1a/pg2 x0a/pg1 vcc c rst/pf2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 20 21 22 23 24 32 31 30 29 28 27 26 25 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 (top view) 16 pins dip-16p-m06 fpt-16p-m06 (top view) 32 pins lcc-32p-m19 the number of usable pins is 16. (top view) 8 pins dip-8p-m03 / fpt-8p-m08
mb95260h/270h/280h series document number: 002-07516 rev. *b page 13 of 92 5. pin description (m b95260h series, 32 pins) (continued) pin no. pin name i/o circuit type* function 1 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 2 pf0 b general-purpose i/o port x0 main clock input oscillation pin 3 vss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6 vcc ? power supply pin 7 c ? capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin this is a dedicated reset pin in mb95f262h/f263h/f264h. 9 p63 d general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 10 p62 d general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 11 nc ? it is an internally connect ed pin. always leave it unconnected. 12 nc ? it is an internally connect ed pin. always leave it unconnected. 13 nc ? it is an internally connect ed pin. always leave it unconnected. 14 nc ? it is an internally connect ed pin. always leave it unconnected. 15 p00 e general-purpose i/o port an00 a/d converter analog input pin 16 p64 d general-purpose i/o port ec1 8/16-bit composite timer ch. 1 clock input pin 17 p01 e general-purpose i/o port an01 a/d converter analog input pin 18 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 19 p03 e general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 14 of 92 (continued) *: for the i/o circuit types, see ?11. i/o circuit type?. pin no. pin name i/o circuit type* function 20 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite time r ch. 0 clock input pin 21 p05 e general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 p06 g general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 p12 h general-purpose i/o port ec0 8/16-bit composite time r ch. 0 clock input pin dbg dbg input pin 24 p07 g general-purpose i/o port int07 external interrupt input pin 25 nc ? it is an internally connected pin. always leave it unconnected. 26 nc ? it is an internally connected pin. always leave it unconnected. 27 nc ? it is an internally connected pin. always leave it unconnected. 28 nc ? it is an internally connected pin. always leave it unconnected. 29 nc ? it is an internally connected pin. always leave it unconnected. 30 nc ? it is an internally connected pin. always leave it unconnected. 31 nc ? it is an internally connected pin. always leave it unconnected. 32 nc ? it is an internally connected pin. always leave it unconnected.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 15 of 92 6. pin description (m b95260h series, 24 pins) (continued) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 nc ? it is an internally connected pin. always leave it unconnected. 3 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 4v ss ? power supply pin (gnd) 5 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 6 pg1 c general-purpose i/o port x0a subclock input oscillation pin 7v cc ? power supply pin 8 c ? capacitor connection pin 9 pf2 a general-purpose i/o port rst reset pin this is a dedicated reset pin in mb95f262h/f263h/f264h. 10 p62 d general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 11 nc ? it is an internally connected pin. always leave it unconnected. 12 p63 d general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 13 p64 d general-purpose i/o port ec1 8/16-bit composite timer ch. 1 clock input pin 14 nc ? it is an internally connected pin. always leave it unconnected. 15 p00 e general-purpose i/o port an00 a/d converter analog input pin 16 p01 e general-purpose i/o port an01 a/d converter analog input pin 17 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 16 of 92 (continued) *: for the i/o circuit types, see ?11. i/o circuit type?. pin no. pin name i/o circuit type* function 18 p03 e general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 19 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 20 p05 e general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 21 p06 g general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 22 p07 g general-purpose i/o port int07 external interrupt input pin 23 nc ? it is an internally connect ed pin. always leave it unconnected. 24 p12 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 17 of 92 7. pin description (m b95260h series, 20 pins) (continued) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 c ? capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin this is a dedicated reset pin in mb95f262h/f263h/f264h. 9 p62 d general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 10 p63 d general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 11 p64 d general-purpose i/o port ec1 8/16-bit composite timer ch. 1 clock input pin 12 p00 e general-purpose i/o port an00 a/d converter analog input pin 13 p01 e general-purpose i/o port an01 a/d converter analog input pin 14 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 15 p03 e general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 18 of 92 (continued) * : for the i/o circuit types, see ?11. i/o circuit type? . pin no. pin name i/o circuit type* function 16 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 17 p05 e general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 18 p06 g general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 19 p07 g general-purpose i/o port int07 external interrupt input pin 20 p12 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 19 of 92 8. pin description (m b95270h series, 8 pins) *: for the i/o circuit types, see ?11. i/o circuit type?. pin no. pin name i/o circuit type* function 1v ss ? power supply pin (gnd) 2v cc ? power supply pin 3 c ? capacitor connection pin 4 pf2 a general-purpose i/o port rst reset pin this pin is a dedicated reset pin in mb95f272h/f273h/f274h. 5 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin ec0 8/16-bit composite timer ch. 0 clock input pin 6 p05 e general-purpose i/o port high-current pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 7 p06 g general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 8 p12 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 20 of 92 9. pin description (m b95280h series, 32 pins) (continued) pin no. pin name i/o circuit type* function 1 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 2 pf0 b general-purpose i/o port x0 main clock input oscillation pin 3 vss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6 vcc ? power supply pin 7 c ? capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin this is a dedicated reset pin in mb95f282h/f283h/f284h. 9 nc ? it is an internally connected pin. always leave it unconnected. 10 nc ? it is an internally connected pin. always leave it unconnected. 11 nc ? it is an internally connected pin. always leave it unconnected. 12 nc ? it is an internally connected pin. always leave it unconnected. 13 nc ? it is an internally connected pin. always leave it unconnected. 14 nc ? it is an internally connected pin. always leave it unconnected. 15 nc ? it is an internally connected pin. always leave it unconnected. 16 nc ? it is an internally connected pin. always leave it unconnected. 17 p01 e general-purpose i/o port an01 a/d converter analog input pin 18 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 19 p03 e general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 20 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 21 of 92 (continued) *: for the i/o circuit types, see ?11. i/o circuit type?. pin no. pin name i/o circuit type* function 21 p05 e general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 p06 g general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 p12 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin 24 p07 g general-purpose i/o port int07 external interrupt input pin 25 nc ? it is an internally connected pin. always leave it unconnected. 26 nc ? it is an internally connected pin. always leave it unconnected. 27 nc ? it is an internally connected pin. always leave it unconnected. 28 nc ? it is an internally connected pin. always leave it unconnected. 29 nc ? it is an internally connected pin. always leave it unconnected. 30 nc ? it is an internally connected pin. always leave it unconnected. 31 nc ? it is an internally connected pin. always leave it unconnected. 32 nc ? it is an internally connected pin. always leave it unconnected.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 22 of 92 10. pin description (m b95280h series, 16 pins) (continued) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 pf2 a general-purpose i/o port rst reset pin this pin is a dedicated reset pin in mb95f282h/f283h/f284h. 8 c ? capacitor connection pin 9 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 10 p01 e general-purpose i/o port an01 a/d converter analog input pin 11 p03 e general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 12 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 23 of 92 (continued) *: for the i/o circuit types, see ?11. i/o circuit type?. pin no. pin name i/o circuit type* function 13 p05 e general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 clock input pin 14 p06 g general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 clock input pin 15 p07 g general-purpose i/o port int07 external interrupt input pin 16 p12 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95260h/270h/280h series document number: 002-07516 rev. *b page 24 of 92 11. i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side ? feedback resistance: approx. 1 m ? ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side ? feedback resistance: approx.10 m ? ? cmos output ? hysteresis input ? pull-up control available n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95260h/270h/280h series document number: 002-07516 rev. *b page 25 of 92 (continued) type circuit remarks d ? cmos output ? hysteresis input e ? cmos output ? hysteresis input ? pull-up control available f ? cmos output ? hysteresis input ?cmos input ? pull-up control available g ? hysteresis input ? cmos output ? pull-up control available h ? n-ch open drain output ? hysteresis input n-ch p-ch digital output digital output standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control hysteresis input digital output
mb95260h/270h/280h series document number: 002-07516 rev. *b page 26 of 92 12. notes on device handling preventing latch-ups when using the device, ensure that the voltage a pplied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withs tand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in ?24.1 absolute maximum ratings? of ?24. elec trical characteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuates ra pidly even though the fluctuation is within the guaranteed opera ting range of the v cc power supply voltage. as a rule of voltage stabilization, suppress volt age fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. notes on using the external clock when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. 13. pin connection treatment of unused pins if an unused input pin is left unconnected, a component may be pe rmanently damaged due to malfunctions or latch-ups. always pul l up or pull down an unused input pin through a resistor of at least 2 k ? . set an unused input/output pin to the output state and leave it unconnected, or set it to the input stat e and treat it the same as an unused input pin. if there is an unused output pin, le ave it unconnected. power supply pins to reduce unnecessary electro-magnetic emissi on, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of a pproximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. dbg pin connect the dbg pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the debug mode due to noise, minimize the di stance between the dbg pin and the v cc or v ss pin when designing the layout of the printed circuit board. the dbg pin should not stay at ?l? level afte r power-on until the reset output is released. rst pin connect the rst pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the rese t mode due to noise, minimi ze the distance between the rst pin and the v cc or v ss pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after pow er-on. in addition, the rese t output of the pf2/rst pin can be enabled by the rstoe bit of the sysc register, and the reset input func tion and the general purpose i/o function can be selected by the rsten bit of the sysc register.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 27 of 92 c pin use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. t he bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. c cs dbg rst dbg/rst /c pins connection diagram
mb95260h/270h/280h series document number: 002-07516 rev. *b page 28 of 92 14. block diagram (mb95260h series) flash with security function (20/12/8 kbyte) ram (496/240 bytes) interrupt controller 8/10-bit a/d converter 8/16-bit composite timer (0) reset with lvd oscillator circuit cr oscillator clock control on-chip debug wild register external interrupt lin-uart port port f 2 mc-8fx cpu internal bus (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) 8/16-bit composite timer (1) (p62 *3 /to10) (p63 *3 /to11) p64/ec1 (p00/an00 to p05 *3 /an05) pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 (p12/dbg) p02/int02 to p07/int07 (p02/sck) (p03/sot) (p04/sin) c v cc v ss *1: pf2 and p12 are n-ch open drain pins. *2: software option *3: p05, p06, p62 and p63 are high-current ports. note: pins in parentheses indicate that functions of those pins are shared among different resources.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 29 of 92 15. block diagram (mb95270h series) flash with security function (20/12/8 kbyte) ram (496/240 bytes) interrupt controller 8/10-bit a/d converter 8/16-bit composite timer (0) reset with lvd cr oscillator clock control on-chip debug wild register external interrupt port port f 2 mc-8fx cpu internal bus (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) p05 *3 /an05, (p04/an04) (p12/dbg) p04/int04, p06 *3 /int06 c v cc v ss *1: pf2 and p12 are n-ch open drain pins. *2: software option *3: p05 and p06 are high-current ports. pf2 *1 /rst *2 note: pins in parentheses indicate that functions of those pins are shared among different resources.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 30 of 92 16. block diagram (mb95280h series) flash with security function (20/12/8 kbyte) ram (496/240 bytes) interrupt controller 8/10-bit a/d converter 8/16-bit composite timer (0) reset with lvd oscillator circuit cr oscillator clock control on-chip debug wild register external interrupt lin-uart port port f 2 mc-8fx cpu internal bus (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) (p01/an01 to p05 *3 /an05) pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 (p12/dbg) p02/int02 to p07/int07 (p02/sck) (p03/sot) (p04/sin) c v cc v ss *1: pf2 and p12 are n-ch open drain pins. *2: software option *3: p05 and p06 are high-current ports. pf2 *1 /rst *2 note: pins in parentheses indicate that functions of those pins are shared among different resources.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 31 of 92 17. cpu core memory space the memory space of the mb95260h/270h/280h se ries is 64 kbyte in size, and consists of an i/o area, a data area, and a program area. the memory space includes areas intended for specific purpos es such as general-purpose regi sters and a vector table. the memory maps of the mb95260h/270h/280h series are shown below. memory maps i/o area access prohibited ram 496 bytes register access prohibited extension i/o area access prohibited flash 20 kbyte 0000 h 0080 h 0090 h 0100 h 0200 h 0280 h 0f80 h 1000 h b000 h ffff h mb95f264h/f264k/f274h/ f274k/f284h/f284k i/o area access prohibited ram 496 bytes register access prohibited access prohibited extension i/o area access prohibited flash 8 kbyte 0000 h 0080 h 0090 h 0100 h 0280 h 0200 h 0f80 h 1000 h b000 h c000 h e000 h ffff h mb95f263h/f263k/f273h/ f273k/f283h/f283k i/o area access prohibited ram 240 bytes register access prohibited extension i/o area access prohibited access prohibited flash 4 kbyte flash 4 kbyte flash 4 kbyte 0000 h 0080 h 0090 h 0100 h 0180 h 0f80 h 1000 h b000 h c000 h f000 h ffff h mb95f262h/f262k/f272h/ f272k/f282h/f282k
mb95260h/270h/280h series document number: 002-07516 rev. *b page 32 of 92 18. i/o map (mb95260h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w 0000x011 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 ch. 0 r/w 00000000 b 0038 h t11cr1 8/16-bit composite timer 11 status control register 1 ch. 1 r/w 00000000 b 0039 h t10cr1 8/16-bit composite timer 10 status control register 1 ch. 1 r/w 00000000 b 003a h to 0048 h ? (disabled) ? ? 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 33 of 92 (continued) address register abbreviation register name r/w initial value 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h to 004f h ? (disabled) ? ? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart receive/trans mit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicati on control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter da ta register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ e control register 0 r/w 00000000 b 0074 h fsr3 flash memory status register 3 r 0000xxxx b 0075 h ? (disabled) ? ? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 34 of 92 (continued) address register abbreviation register name r/w initial value 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data sett ing register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 stat us control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 stat us control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 time r mode control register ch. 0 r/w 00000000 b 0f97 h t11cr0 8/16-bit composite timer 11 stat us control register 0 ch. 1 r/w 00000000 b 0f98 h t10cr0 8/16-bit composite timer 10 stat us control register 0 ch. 1 r/w 00000000 b 0f99 h t11dr 8/16-bit composite timer 11 data register ch. 1 r/w 00000000 b 0f9a h t10dr 8/16-bit composite timer 10 data register ch. 1 r/w 00000000 b 0f9b h tmcr1 8/16-bit composite timer 10/11 time r mode control register ch. 1 r/w 00000000 b 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 1xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 35 of 92 (continued) r/w access symbols initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configurati on register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 36 of 92 19. i/o map (mb95270h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w 0000x011 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock contro l register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h ? (disabled) ? ? 0017 h ? (disabled) ? ? 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h ? (disabled) ? ? 002b h ? (disabled) ? ? 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h ? (disabled) ? ? 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 ch. 0 r/w 00000000 b 0038 h ? (disabled) ? ? 0039 h ? (disabled) ? ? 003a h to 0048 h ? (disabled) ? ? 0049 h ? (disabled) ? ?
mb95260h/270h/280h series document number: 002-07516 rev. *b page 37 of 92 (continued) address register abbreviation register name r/ w initial value 004a h eic20 external interrupt circuit control register ch. 4 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6 r/w 00000000 b 004c h to 004f h ? (disabled) ? ? 0050 h ? (disabled) ? ? 0051 h ? (disabled) ? ? 0052 h ? (disabled) ? ? 0053 h ? (disabled) ? ? 0054 h ? (disabled) ? ? 0055 h ? (disabled) ? ? 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 0000xxxx b 0075 h ? (disabled) ? ? 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (r p) and direct bank pointer (dp) ? ? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ? (disabled) ? ? 007c h ? (disabled) ? ? 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 38 of 92 (continued) address register abbreviation register name r/w initial value 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 stat us control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 stat us control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 time r mode control register ch. 0 r/w 00000000 b 0f97 h ? (disabled) ? ? 0f98 h ? (disabled) ? ? 0f99 h ? (disabled) ? ? 0f9a h ? (disabled) ? ? 0f9b h ? (disabled) ? ? 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h ? (disabled) ? ? 0fbd h ? (disabled) ? ? 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 1xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configurati on register r/w 11000011 b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 39 of 92 (continued) r/w access symbols initial value symbols note: do not write to an address that is ?( disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned . address register abbreviation register name r/w initial value 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 40 of 92 20. i/o map (mb95280h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w 0000x011 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h ? (disabled) ? ? 0017 h ? (disabled) ? ? 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 ch. 0 r/w 00000000 b 0038 h ? (disabled) ? ? 0039 h ? (disabled) ? ? 003a h to 0048 h ? (disabled) ? ? 0049 h eic10 external interrupt circuit cont rol register ch. 2/ch. 3 r/w 00000000 b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 41 of 92 (continued) address register abbreviation register name r/w initial value 004a h eic20 external interrupt circuit cont rol register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit cont rol register ch. 6/ch. 7 r/w 00000000 b 004c h to 004f h ? (disabled) ? ? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart receive/trans mit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicati on control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory status register 3 r 0000xxxx b 0075 h ? (disabled) ? ? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ?
mb95260h/270h/280h series document number: 002-07516 rev. *b page 42 of 92 (continued) address register abbreviation register name r/w initial value 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data sett ing register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 stat us control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 stat us control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 time r mode control register ch. 0 r/w 00000000 b 0f97 h ? (disabled) ? ? 0f98 h ? (disabled) ? ? 0f99 h ? (disabled) ? ? 0f9a h ? (disabled) ? ? 0f9b h ? (disabled) ? ? 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 1xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b
mb95260h/270h/280h series document number: 002-07516 rev. *b page 43 of 92 (continued) r/w access symbols initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configuration register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 44 of 92 21. interrupt source table (mb95260h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high external interrupt ch. 5 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] lin-uart (reception) irq07 ffec h ffed h l07 [1:0] lin-uart (transmission) irq08 ffea h ffeb h l08 [1:0] ?irq09ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] low
mb95260h/270h/280h series document number: 002-07516 rev. *b page 45 of 92 22. interrupt source table (mb95270h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high ? irq01 fff8 h fff9 h l01 [1:0] ? irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 ? irq03 fff4 h fff5 h l03 [1:0] ? ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] ? irq07 ffec h ffed h l07 [1:0] ? irq08 ffea h ffeb h l08 [1:0] ?irq09ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] low
mb95260h/270h/280h series document number: 002-07516 rev. *b page 46 of 92 23. interrupt source table (mb95280h series) interrupt source interrupt re- quest num- ber vector table address bit name of interrupt level setting register priority order of in- terrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high external interrupt ch. 5 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] lin-uart (reception) irq07 ffec h ffed h l07 [1:0] lin-uart (transmission) irq08 ffea h ffeb h l08 [1:0] ?irq09ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d c onverter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] low
mb95260h/270h/280h series document number: 002-07516 rev. *b page 47 of 92 24. electrical characteristics 24.1 absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss - 0.3 v ss + 6 v input voltage* 1 v i v ss - 0.3 v ss + 6 v *2 output voltage* 1 v o v ss - 0.3 v ss + 6 v *2 maximum clamp current i clamp - 2 + 2 ma applicable to specific pins *3 total maximum clamp current |i clamp | ? 20 ma applicable to specific pins *3 ?l? level maximum output current i ol1 ? 15 ma other than p05, p06, p62 and p63 *4 i ol2 15 p05, p06, p62 and p63 *4 ?l? level average current i olav1 ? 4 ma other than p05, p06, p62 and p63 *4 average output current= operating current operating ratio (1 pin) i olav2 12 p05, p06, p62 and p63 *4 average output current= operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ?50 ma total average output current= operating current operating ratio (total number of pins) ?h? level maximum output current i oh1 ? - 15 ma other than p05, p06, p62 and p63 *4 i oh2 - 15 p05, p06, p62 and p63 *4 ?h? level average current i ohav1 ? - 4 ma other than p05, p06, p62 and p63 *4 average output current= operating current operating ratio (1 pin) i ohav2 - 8 p05, p06, p62 and p63 *4 average output current= operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? - 100ma ?h? level total average output current i ohav ? - 50 ma total average output current= operating current operating ratio (total number of pins) power consumption pd ? 320 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c
mb95260h/270h/280h series document number: 002-07516 rev. *b page 48 of 92 (continued) *1: these parameters are based on the condition that v ss is 0.0 v. *2: v i and v o must not exceed v cc + 0.3 v. v i must not exceed the rated voltage. howeve r, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: applicable to the following pins: p00 to p07, p62 to p64, pg 1, pg2, pf0, pf1 (p00, p62, p 63 and p64 are only available on mb95f262h/f262k/f263h/f263k/f264h/f264k. p01, p02, p03, p07, pg1, pg2, pf0 and pf1 are only available on mb95f262h/f262k/f263h/f263k/f264h/f264k/f282h/f282k/f283h/f283k/f284h/f284k.) ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a li miting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when t he hv (high voltage) signal is input is below the standard value, irres pective of whether the current is transient current or station ary current. ? when the microcontroller drive current is low, such as in lo w power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcontroller power supply is off (not fixed at 0 v), since power is suppl ied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since pow er is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit : *4: p62 and p63 are only available on mb95f262h/f262k/f263h/f263k/f264h/f264k. warning: semiconductor devices can be perm anently damaged by application of stress (v oltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor input/output equivalent circuit
mb95260h/270h/280h series document number: 002-07516 rev. *b page 49 of 92 24.2 recommended operating conditions (v ss = 0.0 v) *1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: the value is 2.88 v when the lo w-voltage detection reset is used. *3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noi se, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warrant ed when the device is oper ated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditio ns, or combinations not represented on the data sheet. users considering application outside the listed condition s are advised to contact thei r representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1 * 2 5.5* 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode smoothing capacitor c s 0.022 1 f *3 operating temperature t a -40 + 85 c other than on-chip debug mode + 5 + 35 on-chip debug mode c cs dbg * since the dbg pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of p12/dbg. *: rst dbg / rst / c pins connection diagram
mb95260h/270h/280h series document number: 002-07516 rev. *b page 50 of 92 24.3 dc characteristics (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) (continued) parameter symbol pin name condition value unit remarks min typ max "h" level input voltage v ihi p04 *1 0.7 v cc ?v cc + 0.3 v when cmos input level (hysteresis input) is selected v ihs p00 to p07, p12, p62 to p64, pf0, pf1, pg1, pg2 *1 0.8 v cc ?v cc + 0.3 v hysteresis input v ihm pf2 ? 0.7 v cc ?v cc + 0.3 v hysteresis input ?l? level input voltage v il p04 *1 v ss - 0.3 ? 0.3 v cc v when cmos input level (hysteresis input) is selected v ils p00 to p07, p12, p62 to p64, pf0, pf1, pg1, pg2 *1 v ss - 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss - 0.3 ? 0.3 v cc v hysteresis input open-drain output application voltage v d pf2, p12 ? v ss - 0.3 ? v ss + 5.5 v ?h? level output voltage v oh1 output pins other than p05, p06, p12, p62, p63, pf2 *2 i oh = - 4 ma v cc - 0.5 ? ? v v oh2 p05, p06, p62, p63 *2 i oh = - 8 ma v cc - 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p05, p06, p62, p63 *2 i ol = 4 ma ? ? 0.4 v v ol2 p05, p06, p62, p63 *2 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc - 5 ? + 5 a when pull-up resistance is disabled pull-up resistance r pull p00 to p07, pg1, pg2 *3*4 v i = 0 v 25 50 100 k ? when pull-up resistance is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf
mb95260h/270h/280h series document number: 002-07516 rev. *b page 51 of 92 (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) (continued) parameter symbol pin name condition value unit remarks min typ max power supply current* 4 i cc v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?1317ma except during flash memory programming and erasing ?33.539.5ma during flash memory programming and erasing ? 15 21 ma at a/d conversion i ccs v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?5.5 9 ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = + 25c ?65153a i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = + 25c ?1084a i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = + 25c ? 5 30 a i ccmcr v cc v cc = 5.5 v f crh = 10 mhz f mp = 10 mhz main cr clock mode ?8.6? ma i ccscr v cc = 5.5 v sub-cr clock mode (divided by 2) t a = + 25c ? 110 410 a
mb95260h/270h/280h series document number: 002-07516 rev. *b page 52 of 92 (continued) (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) *1: the input level of p04 can be switched between ?cmos input le vel? and ?hysteresis input level?. the input level selection re gister (ilsr) is used to switch be tween the two input levels. *2: p62 and p63 are only available on mb95f262h/f262k/f263h/f263k/f264h/f264k. *3: p00 is only available on mb95f262h/f262k/f263h/f263k/f264h/f 264k. p01, p02, p03, p07, pg 1 and pg2 are only available on mb95f262h/f262k/f263h/f263k/f264h/f264 k/f282h/f282k/f283h/ f283k/f284h/f284k. *4: ? the power supply current is determined by the external cloc k. when the low-voltage detecti on option is selected, the power- supply current will be the sum of adding the current c onsumption of the low-voltage detection circuit (i lvd ) to one of the value from i cc to i cch . in addition, when both the low-voltage detection option and the cr oscillator are selected, the power supply current will be the sum of adding up the current consum ption of the low-voltage detection circuit, the current consumption of the cr oscilla tors (i crh , i crl ) and a specified value. in on-chip debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumpti on therefore increases accordingly. ? see ?24.4. ac characteristics: 24.4.1. clock timing? for f ch and f cl . ? see ?24.4. ac characteristics: 24.4.2 . source clock / machine clock? for f mp and f mpl . parameter symbol pin name condition value unit remarks min typ max power supply current* 4 i ccts v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz time-base timer mode t a = + 25c ?1.1 3 ma i cch v cc = 5.5 v substop mode t a = + 25c ? 3.5 22.5 a main stop mode for single external clock selection i lvd v cc current consumption for low-voltage detection circuit only ?3754a i crh current consumption for the main cr oscillator ?0.50.6ma i crl current consumption for the sub-cr oscillator oscillating at 100 khz ?2072a
mb95260h/270h/280h series document number: 002-07516 rev. *b page 53 of 92 24.4 ac characteristics 24.4.1 clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = -40c to + 85c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1 : open 1 ? 12 mhz when the main external clock is used x0, x1 *1 1 ? 32.5 mhz f crh ?? 9.7 10 10.3 mhz when the main cr clock is used* 2 3.3 v vcc 5.5 v(-40 c t a + 40 c) 2.4 v vcc < 3.3 v(0 c t a + 40 c) 7.76 8 8.24 mhz 0.97 1 1.03 mhz 9.55 10 10.45 mhz when the main cr clock is used* 2 3.3 v vcc 5.5 v ( + 40 c < t a + 85 c) 7.64 8 8.36 mhz 0.955 1 1.045 mhz 9.5 10 10.5 mhz when the main cr clock is used* 2 2.4 v vcc < 3.3 v (-40 c t a < 0 c, + 40 c < t a + 85 c) 7.688.4mhz 0.95 1 1.05 mhz 9.7 10 10.3 mhz when the main cr clock is used* 3 2.4 v vcc 5.5 v(0 c t a + 40 c) 7.76 8 8.24 mhz 0.97 1 1.03 mhz 9.5 10 10.5 mhz when the main cr clock is used* 3 2.4 v vcc 5.5 v (-40 c t a < 0 c, ? 40 c < t a ? 85 c) 7.688.4mhz 0.95 1 1.05 mhz f cl x0a, x1a ? ? 32.768 ? khz when the sub oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 200 khz when the sub cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1 : open 83.4 ? 1000 ns when the external clock is used x0, x1 *1 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used
mb95260h/270h/280h series document number: 002-07516 rev. *b page 54 of 92 (continued) (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = -40c to + 85c) *1: the external clock signal is input to x0 and the inverted external clock signal to x1. *2: these specifications are not applicable to the fo llowing products: mb95f272hph, mb95f272kph, mb95f273hph, mb95f273kph, mb95f274hph, mb95f274kph, mb95f282hph, mb95f282kph, mb95f283hph, mb95f283kph, mb95f284hph and mb95f284kph. *3: these specifications are only applicable to the following products: mb95f272hph, mb95f272kph, mb95f273hph, mb95f273kph, mb95f274hph, mb95f274kph, mb95f282hph, mb95f282kph, mb95f283hph, mb95f283kph, mb95f284hph and mb95f284kph. parameter symbol pin name condition value unit remarks min typ max input clock pulse width t wh1 t wl1 x0 x1 : open 33.4 ? ? ns when the external clock is used, the duty ratio should range between 40% and 60%. x0, x1 *1 12.4 ? ? ns t wh2 t wl2 x0a ? ? 15.2 ? s input clock rise time and fall time t cr t cf x0 x1 : open ? ? 5 ns when the external clock is used x0, x1 *1 ? ? 5 ns cr oscillation start time t crhwk ? ? ? ? 80 s when the main cr clock is used t crlwk ? ? ? ? 10 s when the sub cr clock is used
mb95260h/270h/280h series document number: 002-07516 rev. *b page 55 of 92 x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf input waveform generated when an external clock (main clock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0 x1 x0 x1 f ch f ch when an external clock is used (x1 is open) x0 x1 open f ch figure of main clock input port external connection x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0a x1a x0a x1a open f cl f cl figure of subclock input port external connection
mb95260h/270h/280h series document number: 002-07516 rev. *b page 56 of 92 24.4.2 source cl ock / machine clock (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) *1: this is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits ( sycc : div1 and div0) . this source clock is divided to become a machine clock according to the division ratio set by the machine clock div ision ratio select bits (sycc : div1 and div0). in addition, a source clock can be selected from the following. ? main clock divided by 2 ? main cr clock ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 100 ? 1000 ns when the main cr clock is used min: f crh = 10 mhz max: f crh = 1 mhz ?61?s when the sub-oscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used 1 ? 10 mhz when the main cr clock is used f spl ? 16.384 ? khz when the sub-oscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 100 ? 16000 ns when the main cr clock is used min: f sp = 10 mhz max: f sp = 1 mhz, divided by 16 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.0625 ? 10 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the sub-oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95260h/270h/280h series document number: 002-07516 rev. *b page 57 of 92 f ch (main oscillation) f crh (main cr clock) f cl (sub-oscillation) f crl (sub- cr clock) sclk (source clock) mclk (machine clock) clock mode select bits (sycc2: rcs1, rcs0) machine clock division ratio select bits (sycc : div1, div0) division circuit 1 1/4 1/8 1/16 divided by 2 divided by 2 divided by 2 schematic diagram of th e clock generation block operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.9 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp ) operating voltage - operating frequency (when t a = -40 ? c to ? 85 ? c) mb95260h/270h/280h (without the on-chip debug function) operating voltage - operating frequency (when t a = -40 ? c to ? 85 ? c) mb95260h/270h/280h (with th e on-chip debug function)
mb95260h/270h/280h series document number: 002-07516 rev. *b page 58 of 92 24.4.3 external reset (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to ? 85c) *1 : see ?24.4.2. source clock / machine clock? for t mclk . *2 : the oscillation time of an oscillator is the time for it to reach 90% of its am plitude. the crystal oscillator has an osci llation time of between several ms and tens of ms. the ceramic oscillator has an oscillation time of between hundreds of s and several ms. the external clock has an oscillation time of 0 ms. the cr o scillator clock has an oscillation time of between several s and several ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation oscillation time of the oscillator* 2 ? 100 ? s in stop mode, subclock mode, sub-sleep mode, watch mode, and power-on 100 ? s in time-base timer mode 0.2 v cc rst 0.2 v cc t rstl t rstl 0.2 v cc 0.2 v cc 100 s x0 internal operating clock 90% of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction internal reset rst in normal operation in stop mode, subclock mode,
mb95260h/270h/280h series document number: 002-07516 rev. *b page 59 of 92 24.4.4 power-on reset (v ss = 0.0 v, t a = -40c to + 85c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 60 of 92 24.4.5 peripheral input timing (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) *1: see ?24.4.2. source cl ock / machine clock? for t mclk . *2: int04, int06 and ec0 are available in all products. *3: int02, int03, int05 and int07 are only available on mb95f262h/f262k/f263h/f263k/f264h/f264k/f282h/f282k/f283h /f283k/f284h/f284k. *4: ec1 is only available on mb95f262h/f262k/f263h/f263k/f264h/f264k. parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int02 to int07 *2,*3 , ec0 *2 , ec1 *4 2 t mclk *1 ?ns peripheral input ?l? pulse width t ihil 2 t mclk *1 ?ns int02 to int07 *2, *3 , ec0 *2 , ec1 *4 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95260h/270h/280h series document number: 002-07516 rev. *b page 61 of 92 24.4.6 lin-uart timing (only available on mb95f262h /f262k/f263h/f263k/f264h/f264k/f282h/f282k/f283h/f283k/f284h /f284k) sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (escr register: sces bit = 0, eccr register: scde bit = 0) (v cc = 5.0 v10%, av ss = v ss = 0.0 v, t a = -40c to + 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?24.4.2. source cl ock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot - 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf + 1 ttl 3 t mclk * 3 - t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95260h/270h/280h series document number: 002-07516 rev. *b page 62 of 92 0.8 v 0.8 v 2.4 v t slovi t ivshi t shixi 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc internal shift clock mode 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t r 0.8 v cc t f external shift clock mode
mb95260h/270h/280h series document number: 002-07516 rev. *b page 63 of 92 sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (escr register: sces bit = 1, eccr register: scde bit = 0) (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?24.4.2. source cl ock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot - 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf + 1 ttl 3 t mclk * 3 - t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95260h/270h/280h series document number: 002-07516 rev. *b page 64 of 92 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc internal shift clock mode 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shove t ivsle t slixe 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shsl t slsh t f 0.8 v cc t r external shift clock mode
mb95260h/270h/280h series document number: 002-07516 rev. *b page 65 of 92 sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (escr register: sces bit = 0, eccr register: scde bit = 1) (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: see ?24.4.2. source cl ock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot - 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns 2.4 v 0.8 v 0.8 v t shovi t sovli t ivsli t slixi 2.4 v 0.8 v 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc
mb95260h/270h/280h series document number: 002-07516 rev. *b page 66 of 92 sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (escr register: sces bit = 1, eccr register: scde bit = 1) (v cc = 5.0 v10%, v ss = 0.0 v, t a = -40c to + 85c) *1:there is a function used to choose whether the sampling of re ception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that delays the output signal of the serial clock for half clock. * 3: see ?24.4.2. source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operating output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot - 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns 0.8 v 2.4 v 2.4 v t slovi t sovhi t ivshi t shixi 2.4 v 0.8 v 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc
mb95260h/270h/280h series document number: 002-07516 rev. *b page 67 of 92 24.4.7 low-voltage detection (v ss = 0.0 v, t a = -40c to + 85c) parameter symbol value unit remarks min typ max release voltage v dl+ 2.52 2.7 2.88 v at power supply rise detection voltage v dl- 2.42 2.6 2.78 v at power supply fall hysteresis width v hys 70 100 ? mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 3000 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 300 ? ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ??300s reset detection delay time t d2 ??20s v hys t d2 t d1 t r t f v cc internal reset signal v on v off v dl+ v dl- time time
mb95260h/270h/280h series document number: 002-07516 rev. *b page 68 of 92 24.5 a/d converter 24.5.1 a/d converter electrical characteristics (v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = -40c to + 85c) parameter symbol value unit remarks min typ max resolution ? ? ? 10 bit total error - 3 ? + 3 lsb linearity error - 2.5 ? + 2.5 lsb differential linear error - 1.9 ? + 1.9 lsb zero transition voltage v ot v ss - 1.5 lsb v ss + 0.5 lsb v ss + 2.5 lsb v full-scale transition voltage v fst v cc - 4.5 lsb v cc - 2 lsb v cc + 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v v cc 5.5 v 1.8 ? 16500 s 4.0 v v cc < 4.5 v sampling time ? 0.6 ? s 4.5 v v cc 5.5 v, with external impedance < 5.4 k ? 1.2 ? s 4.0 v v cc < 4.5 v, with external impedance < 2.4 k ? analog input current i ain - 0.3 ? + 0.3 a analog input voltage v ain v ss ?v cc v
mb95260h/270h/280h series document number: 002-07516 rev. *b page 69 of 92 24.5.2 notes on using the a/d converter external impedance of analog input and its sampling time the a/d converter has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the an alog voltage charged to the capacitor of the internal sample and hol d circuit is insufficient, adversely affecting a/d conversion pr ecision. therefore, to satisfy the a/d conversion precision standard, consid ering the relationship between the external impedance and minimum sampling time, either adjust the register value and oper ating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. comparator analog input during sampling: on note: the values are reference values. ~ ~ ~ ~ 4.5 v < v cc < 5.5 v : r 1.95 k (max), c 17 pf (max) ~ ~ ~ ~ < 4.0 v v cc < 4.5 v : r 8.98 k (max), c 17 pf (max) r c analog input equivalent circuit [external impedance = 0 k to 100 k ] external impedance [k ] external impedance [k ] minimum sampling time [ s] minimum sampling time [ s] [external impedance = 0 k to 20 k ] 100 90 80 70 60 50 40 30 20 10 0 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 101214 1 0 234 (v cc > 4.5 v) (v cc > 4.0 v) (v cc > 4.5 v) (v cc > 4.0 v) relationship between external impedance and minimum sampling time
mb95260h/270h/280h series document number: 002-07516 rev. *b page 70 of 92 24.5.3 definitions of a/d converter terms resolution it indicates the level of analog variation t hat can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?00 0000 0000? ??? ?00 0000 0001?) of a device to the full-scale transition point (?11 1111 1111? ??? ?11 1111 1110?) of the same device. differential linear error (unit: lsb) it indicates how much the input voltage required to chang e the output code by 1 lsb dev iates from an ideal value. total error (unit: lsb) it indicates the difference between an actual value and a theoreti cal value. the error can be caused by a zero transition error , a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v ss v fst ideal i/o characteristics v cc 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h digital output digital output 2 lsb v ot 1 lsb 0.5 lsb total error analog input analog input 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from (n - 1) h to n h {1 lsb (n-1) + 0.5 lsb} v nt v ss v cc total error of digital output n v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] = v cc - v ss 1024 (v) 1 lsb =
mb95260h/270h/280h series document number: 002-07516 rev. *b page 71 of 92 (continued) zero transition error linearity error full-scale transition error 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h digital output differential linear error of digital output n v (n+1)t - v nt 1 lsb - 1 = linearity error of digital output n v nt - {1 lsb n + v ot } 1 lsb = digital output analog input 001 h 002 h 3fc h 3fd h 003 h 3fe h 3ff h 004 h actual conversion characteristic actual conversion characteristic v ot (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc analog input v ss v cc digital output analog input v ss v cc ideal characteristic {1 lsb n + v ot } actual conversion characteristic ideal characteristic actual conversion characteristic v ot (measurement value) v nt differential linearity error (n - 2) h (n - 1) h n h (n + 1) h digital output analog input v ss v cc actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n+1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from (n - 1) h to n h v ot (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc - 2 lsb [v] v fst (measurement value) ideal characteristic
mb95260h/270h/280h series document number: 002-07516 rev. *b page 72 of 92 24.6 flash memory program/erase characteristics *1: t a = + 25c, v cc = 5.0 v, 100000 cycles *2: t a = + 85c, v cc = 3.0 v, 100000 cycles * 3: this value is converted from the result of a technology reliability assessment. (the value is converted from the result of a high temperature accelerated test using the arrhenius equation with the average te mperature being + 85c) . parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.2* 1 0.5* 2 s the time of writing 00 h prior to erasure is excluded. sector erase time (16 kbyte sector) ?0.5* 1 7.5* 2 s the time of writing 00 h prior to erasure is excluded. byte writing time ? 21 6100* 2 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 3.0 ? 5.5 v flash memory data retention time 20* 3 ? ? year average t a = + 85c
mb95260h/270h/280h series document number: 002-07516 rev. *b page 73 of 92 25. sample characteristics power supply curre nt temperature (continued) 0 5 10 15 20 234567 vcc [v] icc [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 5 10 15 20 ? 50 0 +50 +100 +150 icc [ma] f mp = 16 mhz f mp = 10 mhz t a [ c] 0 5 10 15 20 234567 vcc [v] i ccs [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 5 10 15 20 ? 50 0 +50 +100 +150 i ccs [ma] t a [ c] f mp = 16 mhz f mp = 10mhz 0 25 50 75 100 234567 vcc [v] icc l [ a] 0 25 50 75 100 ? 50 0 +50 +100 +150 icc l [ a] t a [ c] icc - vcc t a = + 25c f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating icc - t a vcc = 5.5 v f mp = 10, 16 mhz (divided by 2) main clock mode with the external clock operating iccs - vcc t a = + 25c f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating iccs - t a vcc = 5.5 v f mp = 10, 16 mhz (divided by 2) main sleep mode with the ex ternal clock operating i ccl - vcc t a = + 25c f mpl = 16 khz (divided by 2) subclock mode with the external clock operating i ccl - t a vcc = 5.5 v f mpl = 16 khz (divided by 2) subclock mode with the external clock operating
mb95260h/270h/280h series document number: 002-07516 rev. *b page 74 of 92 (continued) 0 10 20 30 40 50 60 70 80 234567 vcc [v] icc ls [ a] 0 10 20 30 40 50 60 70 80 ? 50 0 +50 +100 +150 icc ls [ a] t a [ c] 0 4 8 12 16 20 234567 vcc [v] icc t [ a] 0 4 8 12 16 20 ? 50 0 +50 +100 +150 icc t [ a] t a [ c] 0 0.2 0.4 0.6 0.8 1 1.2 1.4 234567 vcc [v] i cts [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 0.2 0.4 0.6 0.8 1 1.2 1.4 ? 50 0 +50 +100 +150 t a [ c] f mp = 16 mhz f mp = 10 mhz i cts [ma] i ccls - vcc t a = + 25c f mpl = 16 khz (divided by 2) subsleep mode with the ex ternal clock operating i ccls - t a vcc = 5.5 v f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating i cct - vcc t a = + 25c f mpl = 16 khz (divided by 2) watch mode with the external clock operating i cct - t a vcc = 5.5 v f mpl = 16 khz (divided by 2) watch mode with the external clock operating i cts - vcc t a = + 25c f mp = 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i cts - t a vcc = 5.5 v f mp = 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating
mb95260h/270h/280h series document number: 002-07516 rev. *b page 75 of 92 (continued) 0 4 8 12 16 20 ? 50 0 +50 +100 +150 icc h [ a] t a [ c] 0 5 10 15 20 234567 vcc [v] i ccmcr [ma] f mp = 10 mhz f mp = 8 mhz f mp = 1 mhz 0 5 10 15 20 ? 50 0 +50 +100 +150 i ccmcr [ma] t a [ c] f mp = 10 mhz f mp = 8 mhz f mp = 1 mhz 0 50 100 150 200 234567 vcc [v] i ccscr [ a] 0 50 100 150 200 ? 50 0 +50 +100 +150 i ccscr [ a] t a [ c] 0 4 8 12 16 20 2345 7 6 vcc [v] icc h [ a] i cch - vcc t a = + 25c f mpl = (stop) substop mode with the external clock stopping i cch - t a vcc = 5.5 v f mpl = (stop) substop mode with the external clock stopping i ccmcr - vcc t a = + 25c f mp = 1, 8, 10 mhz (no division) main clock mode with the main cr clock operating i ccmcr - t a vcc = 5.5 v f mp = 1, 8, 10 mhz (no division) main clock mode with the main cr clock operating i ccscr - vcc t a = + 25c f mpl = 50 khz (divided by 2) subclock mode with the sub-cr clock operating i ccscr - t a vcc = 5.5 v f mpl = 50 khz (divided by 2) subclock mode with the sub-cr clock operating
mb95260h/270h/280h series document number: 002-07516 rev. *b page 76 of 92 input voltage v ihi - v cc and v ili - v cc t a =+25c v cc [v] v ihi /v ili [v] 234567 5 4 3 2 1 0 v ihi v ili v ihs - v cc and v ils - v cc t a =+25c v cc [v] v ihs /v ils [v] 234567 5 4 3 2 1 0 v ils v ihs v ihm - v cc and v ilm - v cc t a =+25c v cc [v] v ihm /v ilm [v] 234567 5 4 3 2 1 0 v ilm v ihm
mb95260h/270h/280h series document number: 002-07516 rev. *b page 77 of 92 output voltage vcc = 2.4 v vcc = 2.7 v vcc = 3.5 v vcc = 4.5 v vcc = 5.0 v vcc = 5.5 v 0 0.2 0.4 0.6 0.8 1 ? 10 ? 8 ? 6 ? 4 ? 2 0 i oh [ma] vcc - v oh1 [v] vcc = 2.4 v vcc = 2.7 v vcc = 3.5 v vcc = 4.5 v vcc = 5.0 v vcc = 5.5 v 0 0.2 0.4 0.6 0.8 1 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 i oh [ma] vcc - v oh2 [v] vcc = 2.4 v vcc = 2.7 v vcc = 3.5 v vcc = 4.5 v vcc = 5.0 v vcc = 5.5 v 0 0.2 0.4 0.6 0.8 1 0246810 i ol [ma] v ol1 [v] vcc = 2.4 v vcc = 2.7 v vcc = 3.5 v vcc = 4.5 v vcc = 5.0 v vcc = 5.5 v 0 0.2 0.4 0.6 024681012 i ol [ma] v ol2 [v] (vcc - v oh1 ) - i oh t a = + 25c (vcc - v oh2 ) - i oh t a = + 25c v ol1 - i ol t a = + 25c v ol2 - i ol t a = + 25c
mb95260h/270h/280h series document number: 002-07516 rev. *b page 78 of 92 pull-up 0 50 100 150 200 250 23456 v cc [v] r pull [k ] r pull -vcc t a = + 25c
mb95260h/270h/280h series document number: 002-07516 rev. *b page 79 of 92 26. mask options no. part number mb95f262h mb95f263h mb95f264h mb95f272h mb95f273h mb95f274h mb95f282h mb95f283h mb95f284h mb95f262k mb95f263k mb95f264k mb95f272k mb95f273k mb95f274k mb95f282k mb95f283k mb95f284k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input
mb95260h/270h/280h series document number: 002-07516 rev. *b page 80 of 92 27. ordering information (continued) part number package mb95f262hwqn-g-sne1 mb95f262hwqn-g-snere1 mb95f262kwqn-g-sne1 mb95f262kwqn-g-snere1 mb95f263hwqn-g-sne1 mb95f263hwqn-g-snere1 mb95f263kwqn-g-sne1 mb95f263kwqn-g-snere1 mb95f264hwqn-g-sne1 mb95f264hwqn-g-snere1 mb95f264kwqn-g-sne1 mb95f264kwqn-g-snere1 32-pin plastic qfn (lcc-32p-m19) mb95f262hp-g-sh-sne2 mb95f262kp-g-sh-sne2 mb95f263hp-g-sh-sne2 mb95f263kp-g-sh-sne2 mb95f264hp-g-sh-sne2 mb95f264kp-g-sh-sne2 24-pin plastic sdip (dip-24p-m07) mb95f262hpf-g-sne2 mb95f262kpf-g-sne2 mb95f263hpf-g-sne2 mb95f263kpf-g-sne2 mb95f264hpf-g-sne2 mb95f264kpf-g-sne2 20-pin plastic sop (fpt-20p-m09) mb95f262hpft-g-sne2 mb95f262kpft-g-sne2 mb95f263hpft-g-sne2 mb95f263kpft-g-sne2 mb95f264hpft-g-sne2 mb95f264kpft-g-sne2 20-pin plastic tssop (fpt-20p-m10) mb95f282hwqn-g-sne1 mb95f282hwqn-g-snere1 mb95f282kwqn-g-sne1 mb95f282kwqn-g-snere1 mb95f283hwqn-g-sne1 mb95f283hwqn-g-snere1 mb95f283kwqn-g-sne1 mb95f283kwqn-g-snere1 mb95f284hwqn-g-sne1 mb95f284hwqn-g-snere1 mb95f284kwqn-g-sne1 mb95f284kwqn-g-snere1 32-pin plastic qfn (lcc-32p-m19) mb95f282hph-g-sne2 mb95f282kph-g-sne2 mb95f283hph-g-sne2 mb95f283kph-g-sne2 mb95f284hph-g-sne2 mb95f284kph-g-sne2 16-pin plastic dip (dip-16p-m06)
mb95260h/270h/280h series document number: 002-07516 rev. *b page 81 of 92 (continued) part number package mb95f282hpf-g-sne1 mb95f282kpf-g-sne1 mb95f283hpf-g-sne1 mb95f283kpf-g-sne1 mb95f284hpf-g-sne1 mb95f284kpf-g-sne1 16-pin plastic sop (fpt-16p-m06) mb95f272hph-g-sne2 mb95f272kph-g-sne2 mb95f273hph-g-sne2 mb95f273kph-g-sne2 mb95f274hph-g-sne2 mb95f274kph-g-sne2 8-pin plastic dip (dip-8p-m03) mb95f272hpf-g-sne2 mb95f272kpf-g-sne2 mb95f273hpf-g-sne2 mb95f273kpf-g-sne2 MB95F274HPF-G-SNE2 mb95f274kpf-g-sne2 8-pin plastic sop (fpt-8p-m08)
mb95260h/270h/280h series document number: 002-07516 rev. *b page 82 of 92 28. package dimension (continued) 24-pin plastic sdip lead pitch 1.778 mm package width package length 6.40 mm 22.86 mm sealing method plastic mold mounting height 4.80 mm max 24-pin plastic sdip (dip-24p-m07) (dip-24p-m07) c 2008-2010 fujitsu semiconductor limited d24066s-c-1-2 #22.86 0.10(.900 .004) index typ. 7.62(.300) 6.40 0.10 (.252 .004) btm e-mark ? 0.04 +.004 ? .002 .010 0.25 +0.10 1 12 24 13 4.80(.189)max +0.20 ? 0.30 +.008 ? .012 3.00 .118 1.778(.070) (.039 . 004) 1.00 0.10 +0.09 ? 0.04 +.004 ? .002 .017 0.43 min 0.50(.020) dimensions in mm (inches). note: the values in parentheses are reference values note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 83 of 92 (continued) 32-pin plastic qfn lead pitch 0.50 mm package width package length 5.00 mm 5.00 mm sealing method plastic mold mounting height 0.80 mm max weight 0.06 g 32-pin plastic qfn (lcc-32p-m19) (lcc-32p-m19) (.010 ) c 2009-2010 fujitsu semiconductor limited c32071s-c-1-2 (.197 .004) 5.00 0.10 5.00 0.10 (.197 .004) (3-r0.20) ((3-r.008)) 0.50(.020) 1pin corner (c0.30(c.012)) 0.75 0.05 (0.20(.008)) index area 0.40 0.05 (.016 .002) +0.03 ? 0.02 ? .001 +.001 0.02 (.001 ) (.138 .004) 3.50 0.10 3.50 0.10 (.138 .004) (typ) (.030 .002) +0.05 ? 0.07 ? .003 +.002 0.25 dimensions in mm (inches). note: the values in parentheses are reference values.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 84 of 92 (continued) 20-pin plastic sop lead pitch 1.27 mm package width package length 7.50 mm 12.70 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 2.65 mm max 20-pin plastic sop (fpt-20p-m09) (fpt-20p-m09) c 2008-2010 fujitsu semiconductor limited f20030s-c-1-2 details of "a" part index 0.10(.004) (.008 .004) 0.20 0.10 ? .007 +.005 .099 ? 0.17 +0.13 2.52 (mounting height) 0~8 (stand off) 0.80 +0.47 ? 0.30 .031 +.019 ? .012 "a" ? .001 +.003 .010 0.25 +0.07 ? 0.02 #12.70 0.10(.500 .004) 11 20 1.27(.050) 1 10 0.25(.010) m ? 0.05 +0.09 0.40 .016 +.004 ? .002 #7.50 0.10 (.295 .004) ? 0.20 +0.40 10.2 .402 +.016 ? .008 btm e-mark dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 85 of 92 (continued) 20-pin plastic tssop lead pitch 0.65 mm package width package length 4.40 mm 6.50 mm lead shape gullwing sealing method plastic mold mounting height 1.20 mm max weight 0.08 g 20-pin plastic tssop (fpt-20p-m10) (fpt-20p-m10) c 2009-2010 fujitsu semiconductor limited f20031s-c-1-2 #6.50 0.10(.256 .004) #4.40 0.10 6.40 0.20 (.252 .008) (.173 .004) 0.10(.004) 0.65(.026) 0.24 0.04 (.009 .002) 1 10 20 11 "a" details of "a" part 0~8 (.024 .006) 0.60 0.15 max 1.20(.047) (mounting height) 0.10 0.05 (stand off) lead no. index btm e-mark (.004 .002) 0.14 +0.05 ?0.04 +.002 ?.002 .006 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 86 of 92 (continued) 16-pin plastic dip lead pitch 2.54 mm sealing method plastic mold 16-pin plastic dip (dip-16p-m06) (dip-16p-m06) c 2006-2010 fujitsu semiconductor limited d16125s-c-1-3 0.25 0.05 (.010 .002) 15 max .770 ? .012 +.008 ? 0.30 +0.20 19.55 index 0.50(.020) min typ. 2.54(.100) (.018 .003) 0.46 0.08 3.00(.118)min 4.36(.172)max 1.52 .060 ? 0 +.012 ? 0 +0.30 max 1.27(.050) typ. 7.62(.300) 6.35 0.25 (.250 .010) .039 0.99 +.012 ? 0 +0.30 ? 0 dimensions in mm (inches). note: the values in parentheses are reference values
mb95260h/270h/280h series document number: 002-07516 rev. *b page 87 of 92 (continued) 16-pin plastic sop lead pitch 1.27 mm package width package length 5.3 10.15 mm lead shape gullwing sealing method plastic mold mounting height 2.25 mm max weight 0.20 g code (reference) p-sop16-5.3 10.15-1.27 16-pin plastic sop (fpt-16p-m06) (fpt-16p-m06) c 2002-2010 fujitsu semiconductor limited f16015s-c-4-9 0.13(.005) m details of "a" part 7.800.40 5.300.30 (.209.012) (.307.016) ?.008 +.010 ?0.20 +0.25 10.15 index 1.27(.050) 0.10(.004) 18 9 16 0.470.08 (.019.003) ?0.04 +0.03 0.17 .007 +.001 ?.002 "a" 0.25(.010) (stand off) 0~8 (mounting height) 2.00 +0.25 ?0.15 .079 +.010 ?.006 0.500.20 (.020.008) 0.600.15 (.024.006) 0.10 +0.10 ?0.05 ?.002 +.004 .004 .400 * 1 * 2 0.10(.004) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * 1 : these dimensions include resin protrusion. note 2) * 2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 88 of 92 (continued) 8-pin plastic dip lead pitch 2.54 mm sealing method plastic mold 8-pin plastic dip (dip-8p-m03) (dip-8p-m03) c 2006-2010 fujitsu semiconductor limited d08008s-c-1-4 0.25 0.05 (.010 .002) 15 max .370 ? .012 +.016 ? 0.30 +0.40 9.40 (.250 .010) 6.35 0.25 index 14 85 0.50(.020) min typ. 2.54(.100) (.018 .003) 0.46 0.08 3.00(.118)min 4.36(.172)max 1.52 .060 ? 0 +.012 ? 0 +0.30 ? 0 ? 0 0.99 +0.30 +.012 .039 .035 0.89 +.014 +0.35 ?. 012 ? 0.30 typ. 7.62(.300) dimensions in mm (inches). note: the values in parentheses are reference values
mb95260h/270h/280h series document number: 002-07516 rev. *b page 89 of 92 (continued) 8-pin plastic sop lead pitch 1.27 mm package width package length 5.30 mm 5.24 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 2.10 mm max 8-pin plastic sop (fpt-8p-m08) (fpt-8p-m08) c 2008-2010 fujitsu semiconductor limited f08016s-c-1-2 details of "a" part #5.30 0.10 (.209 .004) index 1.27(.050) 1 4 5 8 0.43 0.05 (.017 .002) "a" (stand off) 0~8 (mounting height) 2.10(.083) max 0.10 +0.15 ? 0.05 ? .002 +.006 .004 7.80 +0.45 ? 0.10 +.018 ? .004 .307 #5.24 0.10 (.206 .004) btm e-mark 0.20 0.05 (.008 .002) +0.10 ? 0.20 0.75 .030 +.004 ? .008 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 90 of 92 29. major changes spansion publication number: ds07?12627?7e note: please see ?document history? about later revised information. page section details 1? changed the family name. f 2 mc-8fx new 8fx 2 features added ?? power-on reset?. 3 product line-up mb95260h series added the parameter ?power-on reset?. 5 product line-up mb95270h series added the parameter ?power-on reset?. 6 product line-up mb95280h series added the parameter ?power-on reset?. 10 pin assignment deleted the hclk1 pin and the hclk2 pin. 11 deleted the hclk1 pin and the hclk2 pin. 13 pin description (mb95260h series, 32 pins) deleted the hclk1 pin and the hclk2 pin. 15 pin description (mb95260h series, 24 pins) deleted the hclk1 pin and the hclk2 pin. 17 pin description (mb95260h series, 20 pins) deleted the hclk1 pin and the hclk2 pin. 18 pin description (mb95270h series, 8 pins) deleted the hclk1 pin and the hclk2 pin. 19 pin description (mb95280h series, 32 pins) deleted the hclk1 pin. 20 deleted the hclk2 pin. 21 pin description (mb95280h series, 16 pins) deleted the hclk1 pin. 22 deleted the hclk2 pin. 27 block diagram (mb95260h series) deleted the hclk1 pin and the hclk2 pin. 28 block diagram (mb95270h series) deleted the hclk1 pin and the hclk2 pin. 29 block diagram (mb95280h series) deleted the hclk1 pin and the hclk2 pin. 52, 53 electrical characteristics 4. ac characteristics (1) clock timing deleted all information about the hclk1 pin and the hclk2 pin in the table. 54 deleted the hclk1 pin and the hclk2 pin in the ? input waveform generated when an external clock (main clock) is used?. deleted the external connection diagram for the hclk1 pin and the hclk2 pin in ? figure of main clock input port external connection?.
mb95260h/270h/280h series document number: 002-07516 rev. *b page 91 of 92 document history document title: mb95260h/270h/280h series new 8fx 8-bit microcontrollers document number: 002-07516 revision ecn orig. of change submission date description of change ** ? akih 07/04/2011 migrated to cypress and assigned document number 002-07516. no change to document contents or format. *a 5199019 akih 04/04/2016 updated to cypress format. *b 5861649 ysat 08/24/2017 adapted new cypress logo
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